1. Field of the Invention
The present invention relates to a III-V group compound semiconductor device such as FET (Field Effect Transistor) and HEMT (High Electron Mobility Transistor), and more particularly to an improvement of a buffer layer in a III-V group compound semiconductor device.
2. Description of the Related Art
For improving a performance of a transistor, it is important to use a material that can transmit more majority carriers with a higher speed. GaAs (gallium arsenide) and InGaAs (indium gallium arsenide) are characterized by that the electron mobility is higher that that of Si (silicon). By utilizing this characteristic, the GaAs and InGaAs are employed frequently in a high-speed operation device. The HEMT (High Electron Mobility Transistor) may be cited for a representative example.
Now, for the field effect transistors such as FET or HEMT, it is common to use an epitaxial wafer comprising a semi-insulating GaAs substrate, a buffer layer and an active layer respectively grown by an epitaxial growth on the semi-insulating GaAs substrate.
FIG. 1 is an explanatory diagram showing a schematic structure of the HEMT.
The HEMT comprises a buffer layer 2, a channel layer 3, a spacer layer 4, a carrier supply layer 5, and a contact layer 7, successively grown on a substrate 1 by a crystal growth method. The contact layer 7 is a layer for forming an electrode (not shown) thereon. The carrier supply layer 5 is a layer for generating free electrons and supplying them to the channel layer 3. The channel layer 3 is a layer through which the free electrons are flown, therefore the channel layer 3 should have a high purity.
The buffer layer 2 is provided for preventing an active layer from being effected by a defect layer generated at an interface between the substrate and the epitaxial crystal. However, it is assumed that an electric current will leak from the active layer into the buffer layer if this buffer layer has a low resistance. Therefore, it is required that the buffer layer 2 is made of the epitaxial crystal having a high resistance. For increasing the resistance of the buffer layer, it is necessary to decrease an impurity concentration of the buffer layer, or to increase a height of a hetero barrier.
Since the current leakage into the buffer layer significantly deteriorates device characteristics of a conventional field effect semiconductor device that is manufactured by growing a p-type buffer layer and a channel layer on a p-type semiconductor substrate by epitaxial grown, an acceptor concentration of the p-type buffer layer is within a range from 5×1016/cm3 to 5×1015/cm3 for suppressing the leakage current. Japanese Patent Laid-Open No. 10-116837 (JP-A-10-116837) discloses such conventional field effect semiconductor device.
However, an issue of a p-type concentration has not been discussed conventionally in connection with a mix crystal ratio of Al and a film thickness of the buffer layer.
The Inventors of the present application have found following facts as a result of their serious studies and efforts. In other words, the problem in the aforementioned disadvantage is that a conductive layer having a low resistance exists at an interface of a semi-insulating substrate and an epitaxial layer of the epitaxial wafer grown by the crystal growth method. When a field effect transistor such as HEMT is manufactured by using such epitaxial wafer, a leakage current is flown between a source electrode and a drain electrode via the conductive layer formed at the interface of the epitaxial layer and substrate. Therefore, the electric characteristics of the transistor will be deteriorated. The cause why the low resistance layer is formed may be assumed as follows. For example, silicon existing everywhere e.g. in the atmosphere and dopant materials remained in a growth furnace may be deposited on a surface of a pre-growth substrate, and may remain on the substrate after growth to become a n-type carrier finally.